8 research outputs found

    Investigations on Ni-Ti-Al ohmic contacts obtained on p-type 4H-SiC

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    International audienceTransfer Length Method (TLM) based-structures were fabricated on 0.8 µm-thick epitaxial p-type Silicon Carbide (4H-SiC) layers. TLM mesas were defined by a 2 µm height using an SF 6 /O 2 reactive ion etching. TLM metal patterns were obtained by a lift-off procedure and electron beam deposition of Ni, Ti, Al and Pt. The patterned samples were annealed in Argon ambient at temperature ranging from 700°C up to 1000°C in a RTA furnace with a rapid heating ramp (up to 50°C/s) to complete the ohmic contact with the p-type SiC layer. Specific contact resistances were extracted from current/voltage measurements. To identify and follow the profile evolution of constituting element in the contacts and at the SiC/contact interface, the ohmic contacts were characterized using Secondary Ion Mass Spectrometry and Energy-Dispersive X-Ray spectroscopy before and after annealing. Ohmic contacts are obtained only for the Ni/Ti/Al and Ni/Ti/Al/Ni stacking layers and not for the Ti/Al/Ti/Ni and Ti/Al/Ti/Pt/Ni compositions. The specific contact resistance of Ni/Ti/Al/Ni stacking layers was observed to decrease from 2.7×10-4  .cm 2 at 700°C and 6.3×10-5 .cm 2 at 750°C to a minimal value of 1.5×10-5  .cm 2 at 800°C. Ohmic contacts are obtained with a reproducibility of 80 %

    1.2 kV pin diodes with SiCrystal epiwafer

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    ISSN: 0255-5476International audienceSilicon carbide devices limitations often originate from the quality of the substrate material. Therefore it is interesting to investigate devices fabricated on alternative source materials. Currently, CREE is the world market leader of SiC wafers. Nowadays, some new companies begin to propose alternative material. The European manufacturer SiCrystal furnishes now some epiwafers for the fabrication of 1,2kV devices. In this paper we present 4H-SiC 1.2 kV pin diodes with a JTE termination realized on a SiCrystal epiwafer. The devices exhibit a blocking voltage of 1.2 kV, a current density of 420 A.cm(-2) and a specific differential series resistance of 4.4 m Omega.cm(2). The yield of fabricated diodes with a breakdown voltage greater 600 V is superior to 75%

    Deep SiC etching with RIE

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    International audienceSiC is currently an important topic in power devices. This new technology leads to lower power losses, faster switching, and higher working temperature. The design of SiC power devices requires the integration of edge termination techniques to obtain a high blocking voltage. The mesa structure approach is one well-established method. It could be used alone or in combination with a Junction Termination Extension (JTE). The mesa consists of a structure that removes material around the pn-junction. Due to the strong Si-C bonds, conventional chemical-wet etching solutions are inefficient on SiC, so plasma methods are required to etch SiC. The presented work is based on the use of an RIE reactor with an SF6/O-2 plasma. Its geometry structure and parameters were optimized. An etch rate of 0.35 mu m/min was obtained without any trenching phenomenon. Trenches deeper than 10 mu m deep were realized with a nickel etching mask that shows a high selectivity. AFM analysis revealed an etched surface as smooth as the initial one. (c) 2006 Elsevier Ltd. All rights reserved

    Deep SiC etching with RIE

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    SUPERLATTICES AND MICROSTRUCTURES 40 (4-6): 388-392 OCT-DEC 2006International audienceSiC is currently an important topic in power devices. This new technology leads to lower power losses, faster switching, and higher working temperature. The design of SiC power devices requires the integration of edge termination techniques to obtain a high blocking voltage. The mesa structure approach is one well-established method. It could be used alone or in combination with a Junction Termination Extension (JTE). The mesa consists of a structure that removes material around the pn-junction. Due to the strong Si-C bonds, conventional chemical-wet etching solutions are inefficient on SiC, so plasma methods are required to etch SiC. The presented work is based on the use of an RIE reactor with an SF6/O-2 plasma. Its geometry structure and parameters were optimized. An etch rate of 0.35 mu m/min was obtained without any trenching phenomenon. Trenches deeper than 10 mu m deep were realized with a nickel etching mask that shows a high selectivity. AFM analysis revealed an etched surface as smooth as the initial one

    Ni-Al Ohmic contact to p-type 4H-SiC

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    International audienceInvestigations on Ni-Al alloys to form ohmic contacts on p-type 4H-SiC are presented in this paper. Several ratios of the Ni/Al contact were examined. Rapid thermal annealing was performed in Argon atmosphere at 400°C during 1 minute, followed by an annealing at 1000°C during 2 minutes. In order to extract the specific contact resistance, transmission line method (TLM) test-structures were fabricated. A specific contact resistance of 3×10-5 Ω.cm2 was obtained reproducibly on p-type layers, with a doping of NA = 1×1019 cm-3 performed by Al2+ ion implantation. The lowest specific contact resistance value measured was 8×10-6 Ω.cm2

    Use of Graphite Cap to Reduce Unwanted Post-Implantation Annealing Effects in SiC

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    International audience6H and 4H-SiC epilayers were Al-implanted at room temperature with multiple energies (ranging from 25 to 300 keV) in order to form p-type layers with an Al plateau concentration of 4.5×1019 cm-3 and 9×1019 cm-3. Post-implantation annealing were performed at 1700 or 1800 °C up to 30 min in Ar ambient. During this process, some samples were encapsulated with a graphite (C) cap obtained by thermal conversion of a spin-coated AZ5214E photoresist. From Atomic Force Microscope measurements, the roughness is found to increase drastically with annealing temperature for unprotected samples while the C capped samples show a preservation of their surface states even for the highest annealing temperature. After 1800°C/30 min annealing, the RMS roughness is 0.46 nm for the lower fluence implanted samples, slightly higher than for unimplanted samples (0.31 nm). Secondary Ion Mass Spectroscopy measurements confirm that the C cap was totally removed from the SiC surface. The total Al-implanted fluence is preserved during postimplantation annealing. A redistribution of the Al dopants is observed at the surface which might be attributed to Si vacancy-enhanced diffusion. An accumulation peak is also observed after annealing at 0.29 9m, depth corresponding to the amorphous/crystalline interface that was determined on the as-implanted samples by Rutherford Backscattering Spectroscopy in channeling mode. The redistribution of the dopants has an impact on their electrical activation. A lower sheet resistance (Rsh= 8 k_) is obtained for samples annealed without capping than for samples annealed with C capping (Rsh= 15 k_ )
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